QuartzHDL v0.2.0 – Write FPGA logic in Julia, run it in Julia, compile it to Verilog

Algorithmic logic in an FPGA often is a port from an implementation in Julia or Python or MATLAB, rewritten as hardware. Porting and testing can be tricky, and debugging the Verilog implementation can be painful. Wouldn’t it be nice if we could just write the hardware description in Julia, pass it inputs and compare the outputs directly from Julia, and poke at various wires in the hardware description from a Julia REPL? That’s what QuartzHDL allows you to do! QuartzHDL keeps the design in the ...